Verification Horizons 2011, June

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SystemVerilogの世界へようこそ、すべては、SystemC v0.9公開から始まった

Verification Horizons 2011, Juneがアップされています。
DAC前の発行のようです。とりあえず、目次は

引用
　　・How Do You Know You Have the Right Tool for the Right Job?
　　・First Principals: Why Bother with This Methodology Stuff, Anyway?
　　・Online UVM/OVM Methodology Cookbook: Registers/Overview
　　・A Methodology for Hardware-Assisted Acceleration of OVM and UVM Testbenches
　　・Combining Algebraic Constraints with Graph-based Intelligent Testbench Automation
　　・Data Management: Is There Such a Thing as an Optimized Unified Coverage Database?
　　・A Unified Verification Flow Using Assertion Synthesis Technology
　　・Benchmarking Functional Verification
　　・Universal Verification Methodology (UVM)-based SystemVerilog Testbench
         for VITAL Models
　　・Efficient Failure Triage with Automated Debug: a Case Study
　　・Are OVM & UVM Macros Evil? A Cost-Benefit Analysis

UVM関連記事満載です。

SystemVerilog関連の読み物としては、Verification Horizons はためになります。

検証、Verification、Mentor、SystemVerilog、UVM、Unified Verification Methodology

Tomさんのブログ(6/25追加)、Verification Horizons DAC Issue Now Available Online