Verification Engineerの戯言
OVMでは、トップテストベンチ(test.sv)は、こんな感じですが、
module test;
`include "ovm.svh"
`include "simple_item.sv"
`include "simple_sequencer.sv"
`include "simple_driver.sv"
`include "simple_seq_lib.sv"
simple_sequencer sequencer;
simple_driver driver;
initial begin
set_config_string("sequencer", "default_sequence", "simple_seq_sub_seqs");
sequencer = new("sequencer", null); sequencer.build();
driver = new("driver", null); driver.build();
driver.seq_item_prod_if.connect_if(sequencer.seq_item_cons_if);
//ovm_default_printer.knobs.reference=0;
ovm_default_printer=ovm_default_tree_printer;
sequencer.print();
driver.print();
fork
run_test();
#2000 global_stop_request();
join
end
endmodule
VMMでのトップテストベンチ(test.sv)は、こんな感じです。似てますね? module test;
`include "vmm.sv"
`include "simple_item.sv"
`include "simple_sequencer.sv"
`include "simple_driver.sv"
`include "simple_seq_lib.sv"
simple_item_scenario_gen sequencer;
simple_driver driver;
initial begin
driver = new("driver");
sequencer = new("sequencer", "", driver.in_chan);
begin
simple_seq_sub_seqs seq = new;
sequencer.scenario_set[0] = seq;
sequencer.stop_after_n_scenarios = 1;
end
driver.start_xactor();
sequencer.start_xactor();
end
initial begin
#2000;
end
endmodule
シーケンスの設定方法は、ちょっと違います。
OVM :
set_config_string("sequencer", "default_sequence", "simple_seq_sub_seqs");
VMM :
begin
simple_seq_sub_seqs seq = new;
sequencer.scenario_set[0] = seq;
sequencer.stop_after_n_scenarios = 1;
end
VMMの場合は、シーケンスの回数も指定できます。検証、Verification、SystemVerilog、VMM、Verification Methodology Manual