VHDLのモジュール定義

実際のところ

内部的なモジュールがentity

entity mymodule is
  Port ( input1 : in STD_LOGIC_VECTOR (3 downto 0);
  output1 : out STD_LOGIC_VECTOR (3 downto 0));
end mymodule;

entityをうけて、振る舞いを定義するのがarchitecture

architecture Behavioral of mymodule is
  begin
  output1 <= input1;
end Behavioral;

一方、componentは外部的なモジュールを定義

component:
COMPONENT mymodule
  PORT(
    input1 : IN std_logic_vector(3 downto 0);
    output1 : OUT std_logic_vector(3 downto 0));
END COMPONENT;

参考もと

VHDL Example Code of Entity and Architecture
https://cdn.sparkfun.com/datasheets/Dev/FPGA/IntroToSpartanFPGABook.pdf