Verilogで順序回路を書くスニペット＠Sublime text

<snippet>
	<content><![CDATA[
always @(posedge CLK) begin
	if(RST)
		${1:LED} <= ${2:8}'h0;
	else if ()
		${1:LED} <= ${2:8}'h0;
	else
		${1:LED} <= ${1:LED} + ${2:8}'h1;
	end
end 
]]></content>
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	<tabTrigger>ff</tabTrigger>
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	<scope>source.verilog</scope>
</snippet>