ChatGPT に頼んで、RISC-V Summit 2025の全体的なスケジュールを表に変換してもらった。
10/21 (Tue) – Member Day / Committees
| セッションタイトル | 登壇者 / 所属 | 分類タグ |
|---|---|---|
| Building RISC-V Together: Progress, Process, and Participation | Rafael Sene (RISC-V Intl.) | KEY / GOV |
| RISC-V 101 (Additional Registration Required) | — | WS / SW / SYS / ISA |
| RISC-V and HPC: Recent Successes, Current Challenges and Future Opportunities | Nick Brown (EPCC, Univ. of Edinburgh) | HPC / SYS / ISA |
| Performance Analysis SIG | — | GOV / SYS / ISA |
| Security Horizontal Committee | — | GOV / SEC |
| Toolchain Features for ISA Evolution | Sam Elliott (Qualcomm) | ISA / SW |
| Unprivileged ISA Committee Update | Earl Kilian (Aril Inc.) | GOV / ISA |
| FP-SIG | — | GOV / ISA |
| Profiles SIG | — | GOV / ISA |
| Supervisor Domains TG / CoVE TG | — | GOV / SYS / SEC |
| CHERI 101 and Standardization Session | Tariq Kurd (Codasip), Helena Handschuh (SCI) | SEC / ISA / WS |
| Profiles SIG & RVM TG Update | — | GOV / ISA |
| HPC SIG | — | GOV / HPC / SYS |
| Cryptographic SIG & Crypto TGs | — | GOV / SEC / ISA |
| Certification Steering Committee Update | J. Ball (Qualcomm), B. Zafar (10xEngineers) | GOV / SEC / ISA |
| The Missing Link: Defining a Standard Firmware Interface for RISC-V MCUs | Alexey Bodkin (Synopsys) | SYS / SW / IOT |
| SoC Infrastructure HC | — | GOV / SYS |
| Security HC Update | A. Dellow (Qualcomm), R. Sahita (Rivos) | GOV / SEC |
| Technology HC Update | J. Duan (Intel), N. Ju (Lyle Tech) | GOV / SYS / ISA |
| Space SIG | — | GOV / AERO |
| SOC Infrastructure HC Update | V. Shanbhogue (Rivos), A. Dellow (Qualcomm) | GOV / SYS |
| Toward a Holistic Compute Platform for Mixed-Criticality RISC-V Platforms | S. Pinto (OSYX), T. Roecker (Infineon) | SYS / SEC / AUTO / IOT |
| Memory Tagging TG | — | SEC / SYS |
| Marketing Committee Meeting | A. Moore (RISC-V Intl.) | GOV / MKT |
| CHERI Meeting | — | GOV / SEC / ISA |
| DTPM SIG | — | GOV / SEC / SYS |
| Privileged Software HC Annual Update | A. Patel & A. Patra (Ventana) | GOV / SYS / SEC |
| RISC-V Documentation: Past Lessons, Present Practices, Future Possibilities | B. Traynor & K. Richter (RVI) | GOV / SW |
| AME TG | — | GOV / ISA / SYS |
| RISC-V CoVE Implementation in Privileged Firmware | S. Zhao (Alibaba DAMO) | SYS / SEC |
| RISC-V Unified Database: Past, Present, Future | P. Clarke (Ventana), D. Hower (Qualcomm) | GOV / ISA / SW |
| Vector SIG Update | J. Moreira (IBM) | GOV / ISA |
| Event Trace TG | — | GOV / SYS / ISA |
| RISC-V AME Progress Update | S. Zhao (Alibaba DAMO) | GOV / ISA |
| The State of the Sail RISC-V Model | P. Mundkur (RVI) | ISA / SYS |
| Scalar Efficiency SIG | — | GOV / ISA |
| Catching Memory Safety Bugs with Hardware Assistance | F. Mayer (Google), D. Gupta (Rivos) | SEC / SYS |
| IME TG Update | J. Moreira (IBM) | GOV / SYS / ISA |
| RiESCUE-D: Framework for Directed Test Development | D. Koshiya (Tenstorrent) | ISA / SYS / SEC |
| Framework for RISCV Certification | N. Ju (Lyle Tech) | SEC / ISA / SYS |
| Machine Readable Travel Documents (PQC TG) | L. Kosmidis (BSC/UPC) | SEC / MKT |
10/22 (Wed) – Main Conference Day 1
| セッションタイトル | 登壇者 / 所属 | 分類タグ |
|---|---|---|
| Keynote: Hardware Innovation to a Thriving RISC-V Ecosystem | Jing Yang (Alibaba DAMO) | KEY / HPC / AI / SYS |
| Keynote: Paving the Road to Datacenter-Scale RISC-V | Martin Dixon (Google) | KEY / HPC |
| Keynote: RISC-V Outperforming Expectations | R. Wawrzyniak (The SHD Group) | KEY |
| Keynote: Securing the Final Frontier: RISC-V in Space and Critical Infrastructure | Ted Speers (Microchip) | KEY / AERO / SEC |
| A RISCy Approach to Microprocessor Technology | David Patterson (UC Berkeley) | KEY / ISA |
| Demo: XuanTie High-Performance Processors | Ren Guo (Alibaba DAMO) | EXPO / HPC / SYS |
| Sponsor Activity: RISC-V With Multi-Threading Available Now! | Akena | |
| Demo: LED Cube Using RISC-V-Based PolarFire SoC FPGA | Microchip Technology Inc | |
| Networking-Native RISC-V Processor for Datacenter | Mark Throndson (MIPS) | HPC / SYS |
| Verifying a Complex RISC-V Processor Using Test Generation and Hardware Emulation Techniques | W. Han & A. Sutton (Synopsys) | ISA / SYS |
| RISC-V is Ready for Intelligent General Computing | C. Su (Andes) | KEY / SYS |
| Accelerating Software Development for High Performance Chiplet-based Using Virtual Prototype | Rae Parnmukh (Tenstorrent) et al. | HPC / SYS / ISA |
| RISC-V Customization After a Tape-out | Z. Přikryl (Codasip), G. Baron (Menta) | ISA / SYS |
| ChipIN Centre: Accelerating India's Journey in RISC-V | V. Reddy & A. Raveendran (C-DAC) | GOV / MKT / SYS |
| Utilizing RISC-V Trace Standards for Efficient Bugfixing and Profiling | D. Griffith (Lauterbach) | ISA / SW / SYS |
| Verifying Out-of-Order RISC-V Vector Extension With Open Source Tools | S. Panandikar & A. Kumar (Tenstorrent) | ISA / AI / SYS |
| Automated Certification & Benchmarking for RISC-V Architectures | E. Pallares (Quintauris) | SEC / ISA |
| Understanding the RISC-V Extensions for AI | J. Simpson (SiFive) | AI / ISA |
| Automating Design Space Exploration Using Advanced Simulation Technologies | K. Lingaard & S. Grove (MIPS) | SYS / ISA |
| The Big-endian RISC-V Linux Adventure | R. Richmond & L. Hunter (Codethink) | SW / SYS |
| Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension | R. Fuhler (Andes) | AI / ISA |
| Enabling RISC-V Success: From Design to Deployment | G. Eide (Siemens) | SYS / MKT |
| Unlocking Potential with TrusteD-V: A RISC-V Rust Software Ecosystem | Y. Singh M (Bosch) | SW / SEC |
| Enabling Intelligent Media Playback - Running VLC With Whisper STT and Qwen T2T on a 40-TO | Y. Liang (DeepComputing) | AI / SW / CONS |
| GPON Solution Demonstrating VOLTHA Stack on RISC-V | P. Mitra (Microchip) | SW / IOT / MKT |
| How NOT To Program an Out-of-order Vector Processor | D. Xie & C. Kerchner (Tenstorrent) | AI / SW / SYS / ISA |
| AI-Ready RISC-V Using On-Chip Monitoring for Performance and Reliability at Scale | Z. Paz (proteanTecs) et al. | AI / SYS |
| Efficient RISC-V Processor Customization: Minimizing Verification Efforts | Z. Přikryl (Codasip) | ISA / SYS |
| Boosting Video Codec with RISC-V Vector Extension | J. Qiu (Alibaba DAMO) & J. Qian (ByteDance) | AI / SW / CONS |
| Next-Gen Edge AI with RISC-V Vector Cores for Vision Applications | F. Zaruba (Axelera AI) | AI / IOT / SYS |
| RISC-V System-level Certification from Verification Foundations | A. Hamid (Breker) | SEC / ISA |
| Nuclei System Technology Releases UX1030H with Full Support for RVA23 | P. Chen (Nuclei System Tech) | SYS / IOT |
| Keynote Lightning Round - Moderated by Andrew Moore | — | KEY |
| Keynote Panel: Linux and RISC-V: Principles for a Winning Partnership | B. Ibrahim (RISE), Red Hat, Canonical, SUSE | KEY / SW |
10/23 (Thu) – Main Conference Day 2
| セッションタイトル | 登壇者 / 所属 | 分類タグ |
|---|---|---|
| Collaboration Breakfast (Google) | — | EXPO |
| Keynote: RISC-V State of the Union | Krste Asanović (RVI) | KEY |
| Keynote: Designing Processors in the Cloud: How Advanced Emulation and AWS Cloud Infrastructure is Reshaping Silicon Development | J. Dahan (AWS) | KEY / HPC / SYS / ISA |
| Keynote: Blockchain, Cryptography, and RISC-V: A New Frontier in Open Development | D. Barbosa (LF DT) | KEY / SEC |
| Keynote: Reimaging the Future of High Performance Computing Catalysed by RISC-V | N. Brown (EPCC) | KEY / HPC |
| Keynote: RISC-V Opportunities at the Edge of AI | M. Shkurti (RVI), E. Doran (Edge AI Foundation) | KEY / AI / IOT |
| Enhancing Embedded Processor Performance THrough Advanced Instruction Fusion | C. Basto & R. Ofir (Synopsys) | ISA / SYS |
| Enhancing OP-TEE for RISC-V: Leveraging IOPMP and Enabling RTOS Integration | B. Yu (Andes) | SEC / SYS |
| Optimizing Real-Time Application Requirements on ARC-V Processors Leveraging RISC-V Extensions | R. Collins (Synopsys) | IOT / SYS |
| Recent Developments in Optimizing Compilers for RISC-V | J. Law (Ventana) | SW / ISA |
| The Future of Ibex - A Production-grade, Open Source 32-bit RISC-V Core | J. Thomson (lowRISC) | IOT / SYS / ISA |
| Enabling System Standby With RISC-V Platform | F. Zhang (Alibaba DAMO) | SYS / IOT |
| PQCP Support for Vector, Future Keccak Extensions | M.-J. Saarinen (Tampere Univ.) | SEC / ISA |
| Unlocking 15% More Performance: A Case Study in LLVM Optimization for RISC-V | M. Gadelha (Igalia) | SW / ISA |
| Unleash RISC-V Future – Tenstorrent’s High Performance Ascalon RISC-V Processor - Now Available! | T. Jones (Tenstorrent) | HPC / AI / SYS |
| Making CHERI Accessible | M. v.d. Maas & J. Thomson (lowRISC) | SEC / ISA |
| SBI V3.0: Fuealin gthe NExt Wave of RISC-V System Software Innovation | A. Patra (Ventana), A. Patel (Rivos) | SYS / SW / ISA |
| RISC-V Performance Delivered | R. Sugumar (Akeana) | HPC / SYS |
| Scaling Data Analytics via Confidential Computing on RISC-V | R. Sahita (Rivos) | SEC / HPC |
| The RISC-V Software Ecosystem: for Latest ISA Extensions | A. Jones (Ventana) | SW / ISA |
| Mission-Critical AI in Space and Sky: SWaP-Constrained Intelligence With RISC-V-Controlled FPGA SoC | D. Ojika (Flapmax), S. Mehrotra (Altera) | AI / AERO / SEC |
| CVA6-CHERI RV64Y Implementation for Commercialization | J. Woodruff & A. Joannou (Capabilities Ltd.) | SEC / ISA / SYS |
| Tiling Support in SiFive AI/ML Software Stack for RISC-V Vector-Matrix Extension (VME) | M. Hsu (SiFive) | AI / SW / ISA |
| Democratizing Inference on Open-weight Models on RISC-V Manycore Accelerators | R. Shaposhnik & T. Dadasheva (Ainekko) | AI / HPC / SYS |
| Unleashing ML Processing Power Through RISC-V Vectors: Applications, Implementations and Verification | B. Barker (Breker) | AI / ISA |
| Running WebLLM in the Browser on RISC-V Toward Lightweight, Local AI Experiences | K. Giori (DeepComputing) | AI / SW / CONS / IOT |
| Defending Against Transient Execution Attacks: Security Enhancements in XuanTie Microarchitecture | X. Qin (Alibaba DAMO) | SEC / SYS |
| The RISE Project: Advancing RISC-V Software | L. Henry (Rivos), N. Egge (Google) | SW / GOV |
| Moving to RISC-V Vector: A Practical Journey of AI Operator Optimization | G. Xu (RISCstar) | AI / ISA |
| RISC-V for Gaming: Emulating x86 on RISC-V | P. Oplopoios (felix86) | CONS / SW / SYS |
| Keynote Panel: Winning the Future of RISC-V Automotive MCU Through Ecosystem Collaboration and Open Standards | Vector, Green Hills, Lauterbach, Synopsys, Infineon | KEY / AUTO |
