Vivado Simulatorを使ってUVMに入門する

もう何回目になるのかわからないが、そろそろUVMを覚えなければならないのでVivado Simulatorを使ってUVMに入門してみよう。

今回はVivado 2023.2を使っている。

参考にしているのは例によって以下のウェブサイトだ：

sites.google.com

• tb_top.sv

`timescale 1ps/1ps

module tb_top;

// UVM class library
`include "uvm_macros.svh"
import uvm_pkg::*;

// uvm user code
`include "sample_model.svh"
`include "sample_test.sv"

/////////////////////////////////////
initial begin
  run_test();
end

endmodule

• sample_test.sv

`timescale 1ps/1ps

`include "uvm_macros.svh"
import uvm_pkg::*;

class sample_test extends uvm_test;

  `uvm_component_utils(sample_test)
  sample_env env;

  function new (string name="sample_test", uvm_component parent=null);
    super.new(name, parent);
  endfunction // new

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    env = sample_env::type_id::create("env", this);
  endfunction // build_phase

  task run_phase(uvm_phase phase);
    uvm_report_info("TEST", "Hello World");
  endtask // run_phase

endclass // sample_test

• model/sample_model.svh

`include "sample_env.sv"

model/sample_env.sv

`include "uvm_macros.svh"
import uvm_pkg::*;

class sample_env extends uvm_env;
  `uvm_component_utils(sample_env)

  function new (string name, uvm_component parent);
    super.new(name,parent);
  endfunction

  task run_phase(uvm_phase phase);
    uvm_report_info("ENV", "Hello ENV");
  endtask
endclass

• Makefie

.PHONY: all
all: build run

SRCS += tb_top.sv
TOP_MODULE += tb_top

.PHONY: build
build:
        xvlog -sv $(SRCS) -L uvm --include ./model
        xelab $(TOP_MODULE) -L uvm -timescale 1ns/1ps

.PHONY: run
run:
        xsim $(TOP_MODULE) -R --testplusarg "UVM_TESTNAME=sample_test"
        
.PHONY: clean
clean:
        rm -rf *.log *.jou *.pb xsim.dir

実行結果は以下のようになった：

UVM_INFO /tools/Xilinx/Vivado/2023.2/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(18648) @ 0: reporter [NO_DPI_TSTNAME] UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI
UVM_INFO @ 0: reporter [RNTST] Running test sample_test...
UVM_INFO /tools/Xilinx/Vivado/2023.2/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(20867) @ 0: reporter [UVM/COMP/NAMECHECK] This implementation of the component name checks requires DPI to be enabled
UVM_INFO @ 0: uvm_test_top [TEST] Hello World
UVM_INFO @ 0: uvm_test_top.env [ENV] Hello ENV
UVM_INFO /tools/Xilinx/Vivado/2023.2/data/system_verilog/uvm_1.2/xlnx_uvm_package.sv(13673) @ 0: reporter [UVM/REPORT/SERVER]